IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test.

The key subject areas of interest are:

Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation.

Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance.

Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues.

Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware.

Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting.

Case Studies: emerging applications, applications in industrial designs, and design frameworks.

IET 计算机与数字技术发表技术论文，介绍数字片上系统设计和电子及嵌入式系统测试各个方面的最新研究和开发工作，包括设计自动化工具（方法、算法和架构）的开发。特别欢迎基于与 CMOS 技术缩小相关的问题的论文。它面向计算机和数字系统设计和测试领域的研究人员、工程师和教育工作者。

感兴趣的关键主题领域是：

设计方法和工具：CAD/EDA 工具、硬件描述语言、高级和架构综合、硬件/软件协同设计、基于平台的设计、3D 堆叠和电路设计、片上系统架构和 IP 核、嵌入式系统、逻辑综合、低功耗设计和功率优化。

仿真、测试和验证：电气和时序仿真、基于仿真的验证、硬件/软件协同仿真和验证、混合域技术建模和仿真、硅后验证、功率分析和估算、互连建模和信号完整性分析、硬件信任和安全性、可测试性设计、嵌入式核心测试、片上系统测试、在线测试、自动测试生成和延迟测试、低功耗测试、可靠性、故障建模和容错。

处理器和系统架构：多核系统、通用和专用处理器、DSP 应用的计算算法、算术和逻辑单元、高速缓存、内存管理、协处理器和加速器、片上系统和网络、嵌入式内核、平台、多处理器、分布式系统、通信协议和低功耗问题。

可配置计算：嵌入式内核、FPGA、快速原型设计、自适应计算、可演化和静态和动态可重构及可重新编程系统、可重构硬件。

针对可变性、功耗和老化的设计：针对可变性、功耗和老化感知设计、内存、FPGA、IP 组件、3D 堆叠、能量收集的设计方法。

案例研究：新兴应用、工业设计中的应用以及设计框架。

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